In a video apparatus such as a video camera, a television, a video tape recorder, etc., an analog signal obtained by scanning an image in a Braun tube or a video capturing device such as, for example, a charge coupled device (or "CCD"), is digitized and stored in some type of storing means. One type of storing means is a digital video memory, which is used for retrieving image data by reading the video signal stored therein and for reconstructing the image on a display screen.
Such a digital video memory is illustrated in FIG. 1, and the operation timing for such a digital video memory is illustrated in FIG. 3. A register circuit used in this type of digital video memory is illustrated in FIG. 2. The register circuit will be explained first referring to FIG. 2.
In the register circuit illustrated in FIG. 2, the source of PMOS transistor MP1 is connected to receive enable signal SRG, and the drain of transistor MP1 is connected to bit line (data line) /RBL, and the gate of transistor MP1 is connected to bit line (data line) RBL. The source of transistor MP2 is connected to receive enable signal SRG, the drain of transistor MP2 is connected to bit line RBL, and the gate of transistor MP2 is connected to bit line/RBL. The source of NMOS transistor MN2 is connected to Vss, the drain of transistor MN2 is connected to bit line RBL, and the gate of transistor MN2 is connected to bit line RBL. The source of transistor NMOS transistor MN1 is connected to Vss, the drain of transistor MN1 is connected to bit line /RBL, and the gate of transistor MN1 is connected to bit line RBL.
Transistors MP1 and MN1 constitute a first inverter, and transistors MP2 and MN2 constitute a second inverter. The first and second inverters operate as a latch.
If a "1" (high level voltage) is applied to bit line RBL, a "0" (low level voltage) is applied to bit line /RBL, and a high level voltage is applied as enable signal SRG, then transistors MN1 and MP2 turn on, and transistors MN2 and MP1 turn off. As a result, this "register" latches the values of bit lines RBL and /RBL.
FIG. 1 is a block diagram of a conventional digital video memory, which consists of dynamic random access memory ("DRAM") 1, register 2 and selector 3.
DRAM 1 includes a plurality of sense amplifiers 4, 5, 6, 7 (SA1, SA2, SA3, . . . SAn), a plurality of bit lines BL and /BL, and a plurality of word lines WL.
Register 2 includes a number of registers 8, 9, 10, 11 (RG1, RG2, RG3, . . . RGn) which are connected to transfer gates (switches) 12, 13, 14, 15, 16, 17, 18 and 19. These transfer switches (MOSFET transistors) are connected to bit lines /BL and BL of the sense amplifiers, respectively, and the gates of the switches are connected to receive transfer signal XF.
Selector 3 has switching transistors 20, 21, 22, 23, 24, 25, . . . 26 and 27, which are NMOS transistors. Bit lines BL and /BL, which are connected to sense amplifiers in DRAM 1, also are connected to sources of transfer switches in register 2. Gates of the transfer switch MOSFETs are connected to receive signal XF and drains of the transfer switch MOSFETs are connected to each register, respectively. Each register performs a latching function, with the enable signal line of each register connected to receive enable signal SRG. The inputs of each of the registers is connected to a drain of a respective transfer switch, and the output of each register is connected to a source of a respective switching transistor of selector 3.
Each pair of gates of the switching transistors connected to each of bit lines RBL and /RBL of selector 3 are connected to receive a corresponding select signal S1-Sn, and the drain of each transistor of the switching transistor pairs is connected to an I/O line, and the other drain of each transistor of the switching transistor pairs is connected to the other I/O line. Bit lines RBL and/RBL are outputs of each register of register 2.
Operation of such a conventional circuit will be explained with reference to the timing chart illustrated in FIG. 3. In read mode, firstly a WL of the DRAM is selected by a row address. Data stored in designated DRAM cells, which are connected to the selected WL, are amplified by the sense amplifiers. As a result, bit lines BL and /BL connected to each of the sense amplifiers are established as "0" or "1" according to the data stored in the DRAM cells.
FIG. 3 illustrates a case in which bit line BL becomes a "1". After signal SRG goes to a "hi-Z" state (or high impedance state) for a short time, each of the signals of bit lines BL and /BL are transferred to the corresponding registers in response to signal XF being a "1." Signal SRG becomes Vcc level, and the input signal of each of bit lines BL and /BL are latched in the respective register. Thereafter, column address signals S1-Sn sequentially select the registers in response to system clock /SC, and thus the data stored in the DRAM are output serially from the registers in accordance with the system clock to data bus I/O.
Before all data in register 2 are output, a new WL in DRAM 1 is selected, and data sensed by the sense amplifiers are established on bit lines BL and /BL. After all data are read out of register 2 through data bus I/O, signal SRG goes hi-Z again, and signal XF becomes "1." Thereafter, signal SRG becomes Vcc level, the input signals of each of bit lines BL and /BL are latched again in the respective register, and column address signals S1-Sn sequentially select the registers, and thus the data stored in the DRAM are output serially from the registers in accordance with the system clock to data bus I/O. In such a way, data stored in the DRAM can be transmitted serially from the register to data bus I/O.
In write mode, signals S1-Sn are enabled sequentially according to the system clock in response to the column address of the DRAM, and serial data appearing on data bus I/O are written in each register, respectively, while the register enable signal SRG holds a "1" state. When data are latched in the register, a WL is selected by a row address of the DRAM, and the data from the register are transferred to cells of the DRAM by transfer signal XF going to a "1" state. After this operation, signal XF goes to a "0" state, and new data are written in the register from the data bus I/O.
As described above, in the conventional digital video memory, while the word line WL is assigned for writing data to DRAM cells, and data are being transferred from the register in order to write data, the register cannot receive new data from data bus I/O.
Digital video memories need to synchronize the data transfer cycle with the system clock and write consecutively in order to receive and store consecutive data. But conventional techniques do not satisfy this need at a speed fast enough to receive consecutive serial data from data bus I/O in a desired manner.